1. Field of Invention
The present invention relates to a manufacturing method of a thin film transistor. More particularly, the present invention relates to a manufacturing method of a low temperature poly-silicon thin film transistor.
2. Description of Related Art
In the early years, the poly-silicon thin film transistor (poly-silicon TFT) is manufactured by executing the solid phase crystallization (SPC) manufacturing process, for its manufacturing temperature reaches as high as 1000° C. Therefore, the quartz substrate with higher melting point is employed. Besides, the cost of the quartz substrate is much higher than that of the glass substrate. Also, due to limitation of size of the substrate, only small-scaled substrates can be developed in the past. With constantly advancing of laser techniques, the excimer laser annealing (ELA) technique is applied in the manufacturing process of the poly-silicon TFT.
The ELA technique mainly utilizes a laser beam for providing lighting on the amorphous silicon layer (a-Si layer) and melting the amorphous silicon layer. Then, after the recrystallization process, the amorphous silicon layer transforms into the poly-silicon layer. Because the poly-silicon TFT is manufactured by using ELA manufacturing process which is executed under the temperature of 600° C., this kind of poly-silicon TFT is also referred as LTPS TFT (low temperature poly-silicon TFT).
FIGS. 1A to 1C schematically show the manufacturing method of LTPS TFT in the prior art. Referring to FIG. 1A, the manufacturing method of LTPS TFT in the prior art comprises the steps as follows. A buffer layer 120 is formed on the substrate 110 and then a first poly-silicon island 130a and a second poly-silicon island 130b are formed on the buffer layer 120. Next, a gate insulating layer 140 is formed on the first poly-silicon island 130a and the second poly-silicon island 130b, and a first gate 150a and a second gate 150b are formed on the gate insulating layer 140.
Referring to FIG. 1B, a photo-resist layer 210 is formed on the substrate 110 for covering the second poly-silicon island 130b and the second gate 150b. Later, a first ion implantation process S110 is performed to form a first source/drain 132a within the first poly-silicon island 130a, and the region between the first source/drain 132a is the first channel region 134a. 
Referring to FIG. 1C, after the formation of the first source/drain 132a, the photo-resist layer 210 is removed. Then, a photo-resist layer 220 is formed on the substrate 110 for covering the first poly-silicon island 130a and the first gate 150a. A second ion implantation process S120 is performed later to form a second source/drain 132b within the second poly-silicon island 130b, and the region between the second source/drain 132b is the second channel region 134b. Following that, the photo-resist layer 220 is removed, and the manufacturing of LTPS TFT in the prior art is finished on the whole up to the present. It's worthy to note that, to form the first source/drain 132a and the second source/drain 132b, it's required that the photo-resist layer 210 and the photo-resist layer 220 to be formed respectively for the manufacturing of LTPS TFT in the prior art. That is, two photolithography processes are required for manufacturing of the first source/drain 132a and the second source/drain 132b. To reduce the amount of photolithography process required, another manufacturing method of LTPS TFT in the prior art was proposed.
FIGS. 2A to 2B schematically show another manufacturing method of LTPS TFT in the prior art. Referring to FIG. 2A, this manufacturing method of LTPS TFT comprises the steps as follows. First, similar to the manufacturing method described previously, a buffer layer 120, a first poly-silicon island 130a, a second poly-silicon island 130b, a gate insulating layer 140, a first gate 150a and a second gate 150b are sequentially formed on the substrate 110. Later, the first ion implantation process S110 is performed to form a first source/drain 132a within the first poly-silicon island 130a, and the region between the first source/drain 132a is the first channel region 134a. It's worthy to note that, the first ion implantation process S110 also implants boron ions into the second poly-silicon island 130.
Then, referring to FIG. 2B, a photo-resist layer 230 is formed on the substrate 110 for covering the first poly-silicon island 130a and the first gate 150a. Next, a second ion implantation process S130 is performed to form a second source/drain 132c within the second poly-silicon island 130b, and the region between the second source/drain 132c is the second channel region 134c. Following that, the photo-resist layer 230 is removed, and the manufacturing of LTPS TFT is completed on the whole up to the present. It's worthy to note that, though one photolithography process can be saved, the boron ion is still implanted into the second poly-silicon island 130b with usage of the first ion implantation process S110. That is, the boron ion previously implanted tends to influence the phosphorous ion implanted by the second ion implantation process S130. Additionally, the two manufacturing methods both cannot provide the lightly doped drain structure that is used for improving the leakage current effect.